Interconnection allocation between functional units and registers in High-Level Synthesis

Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min You Wu

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Data path connection elements usually consume a significant amount of both power and area on a VLSI chip. In this paper, we focus on the interconnection allocation problem conducted after operation scheduling and binding in High-Level Synthesis, aimed at minimum interconnection complexity, power consumption and area cost. During interconnection allocation, the port assignment step, that connects the registers to the operator ports through multiplexers (MUXes), is extraordinarily crucial to the final result in terms of the interconnection complexity. We formulate the port assignment problem for binary commutative operators as a bipartite graph partition problem followed by a vertex cover, and adopt the Fiduccia and Mattheyses (FM) Algorithm to iteratively improve the partition by moving or swapping the graph vertices. The experimental results show that our proposed algorithm is able to achieve 35.9% optimality increasing and 33.1% execution time reduction compared with the previous works.

本文言語English
ホスト出版物のタイトルProceedings of International Conference on ASIC
出版社IEEE Computer Society
ISBN(印刷版)9781467364157
DOI
出版ステータスPublished - 2013
イベント2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen
継続期間: 2013 10 282013 10 31

Other

Other2013 IEEE 10th International Conference on ASIC, ASICON 2013
CityShenzhen
Period13/10/2813/10/31

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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