ISDN SUBSCRIBER LOOP TRANSMISSION SYSTEM BASED ON A TWO-CHIP APPROACH.

M. Fukuda, T. Tsuda, T. Watanabe, T. Gotohda, H. Gambe

    研究成果: Conference contribution

    抄録

    A 144-kb/s digital subscriber loop (DSL) transmission system has been developed using two CMOS LSIs, a programmable multiplexing processor, and an echo canceler. The system uses AMI (automatic mark inversion) line code and a unique frame format for stable timing extraction. Experiments have shown that the system is capable of error-free bidirectional transmission over more than 6 km on a 0. 5-mm-diameter cable at 160 kb/s. The features of the multiplexer-processor and the echo-canceller LSIs, the DSL functions, and some performance characteristics of the system are discussed.

    本文言語English
    ホスト出版物のタイトルUnknown Host Publication Title
    Place of PublicationTokyo, Jpn
    出版社Ohmsha Ltd
    ページ1741-1745
    ページ数5
    ISBN(印刷版)4274031888
    出版ステータスPublished - 1987

    ASJC Scopus subject areas

    • 工学(全般)

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