Lagrangian relaxation based register placement for high-performance circuits

Mei Fang Chiang*, Takumi Okamoto, Takeshi Yoshimura

*この研究の対応する著者

研究成果: Conference contribution

抄録

To achieve low-skew clock distribution, clock tree synthesis (CTS) for local clock optimization is used so far. Challenged by the increasing design complexity and performance demand, a new strategy for local clock optimization is used along with register placement for high-performance circuits. Special local clock distribution is used and registers are legalized to fit required skew. In this paper, we study the register placement problem and formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph. Then, we propose a novel Lagrangian relaxation based algorithm. By relaxing the overlap conflict constraints, the problem is transformed into a minimum weighted bipartite matching problem. Experiments show that our method can efficiently place all registers without overlaps with minimized total register movement.

本文言語English
ホスト出版物のタイトルProceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
ページ511-516
ページ数6
DOI
出版ステータスPublished - 2009
イベント10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA
継続期間: 2009 3 162009 3 18

Other

Other10th International Symposium on Quality Electronic Design, ISQED 2009
CitySan Jose, CA
Period09/3/1609/3/18

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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