A well-source structure that provides a design goal for enhancing latch-up immunity in VLSI full CMOS RAM without additional fabrication steps and performance degradations is described. The key features are to supply a cell power charge from n-well and to arrange cell power lines in such a way as to prevent the parasitic p-n-p transistor from turning on. The availability of the well-source structure was examined by using test devices and 64-kb full-CMOS RAM chips fabricated with 2- mu m n-well technology. No latchup was induced in a cell array portion with the well-source structure. Sixfold increase in the latchup immunity was observed for the RAM with the well-source structure versus the RAM with the conventional cell design.
|ジャーナル||IEEE Journal of Solid-State Circuits|
|出版ステータス||Published - 1987 8|
ASJC Scopus subject areas
- Electrical and Electronic Engineering