Layer assignment and equal-length routing for disordered pins in PCB Design

Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe

研究成果: Article査読

2 被引用数 (Scopus)


In recent printed circuit board (PCB) design, due to the high density of integration, the signal propagation delay or skew has become an important factor for a circuit performance. As the routing delay is proportional to the wire length, the controllability of the wire length is usually focused on. In this research, a heuristic algorithm to get equal-length routing for disordered pins in PCB design is proposed. The approach initially checks the longest common subsequence of source and target pin sets to assign layers for pins. Single commodity flow is then carried out to generate the base routes. Finally, considering target length requirement and available routing region, R-flip and C-flip are adopted to adjust the wire length. The experimental results show that the proposed method is able to obtain the routes with better wire length balance and smaller worst length error in reasonable CPU times.

ジャーナルIPSJ Transactions on System LSI Design Methodology
出版ステータスPublished - 2015 2月 1

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 電子工学および電気工学


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