Live demonstration: FPGA based 3840×2160 video decoding and displaying system

Haoming Zhang, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    抄録

    A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display module in different FPGA board and try to use two off-chip memory of the two boards, in order to provide more memory bandwidth.

    本文言語English
    ホスト出版物のタイトルIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    出版社Institute of Electrical and Electronics Engineers Inc.
    ページ169-170
    ページ数2
    2015-February
    February
    DOI
    出版ステータスPublished - 2015 2 5
    イベント2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
    継続期間: 2014 11 172014 11 20

    Other

    Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
    国/地域Japan
    CityIshigaki Island, Okinawa
    Period14/11/1714/11/20

    ASJC Scopus subject areas

    • 電子工学および電気工学

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