Look up table compaction based on folding of logic functions

Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe

研究成果: Article

抜粋

The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

元の言語English
ページ(範囲)2701-2707
ページ数7
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E85-A
発行部数12
出版物ステータスPublished - 2002 12

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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  • これを引用

    Kimura, S., Ishii, A., Horiyama, T., Nakanishi, M., Kajihara, H., & Watanabe, K. (2002). Look up table compaction based on folding of logic functions. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E85-A(12), 2701-2707.