Look up table compaction based on folding of logic functions

Shinji Kimura*, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe


研究成果: Article査読


The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
出版ステータスPublished - 2002 12

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学


「Look up table compaction based on folding of logic functions」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。