TY - JOUR
T1 - Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
AU - Shimizu, Kazunori
AU - Togawa, Nozomu
AU - Ikenaga, Takeshi
AU - Goto, Satoshi
PY - 2008
Y1 - 2008
N2 - Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation, (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.
AB - Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation, (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.
KW - Clock gated shift register for intermediate message
KW - Intermediate
KW - Low-density parity-check code
KW - Message compression technique
KW - Message-passing algorithm
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U2 - 10.1093/ietfec/e91-a.4.1054
DO - 10.1093/ietfec/e91-a.4.1054
M3 - Article
AN - SCOPUS:78049352399
VL - E91-A
SP - 1054
EP - 1061
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 4
ER -