Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Kazunori Shimizu*, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Article査読

抄録

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation, (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

本文言語English
ページ(範囲)1054-1061
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
4
DOI
出版ステータスPublished - 2008 1月 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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