Low power placement and routing for the coarse-grained power gating FPGA architecture

Ce Li, Yiping Dong, Takahiro Watanabe

研究成果: Article

1 引用 (Scopus)

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Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained power gating to reduce power consumption. The new placement algorithm and routing resource graph for sleep regions is also presented. After enhancing the CAD framework, a detailed discussion is given under different region size supported by the new FPGA architecture. As a result, our proposed FPGA architecture combined with the new placement and routing algorithm can reduce 19.4% in the total power consumption compared with the traditional FPGA. By using our proposed method, FPGA is promising to be widely applied to portable devices.

元の言語English
ページ(範囲)2519-2527
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E94-A
発行部数12
DOI
出版物ステータスPublished - 2011 12

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

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