A 0.25 μm W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 1996 12 1|
|イベント||Proceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA|
継続期間: 1996 12 8 → 1996 12 11
ASJC Scopus subject areas