Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Nozomu Togawa*, Masao Sato, Tatsuo Ohtsuki

*この研究の対応する著者

研究成果: Paper査読

抄録

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

本文言語English
ページ554-559
ページ数6
出版ステータスPublished - 1994 12月 1
イベントProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan
継続期間: 1994 12月 51994 12月 8

Other

OtherProceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
CityTaipei, Taiwan
Period94/12/594/12/8

ASJC Scopus subject areas

  • 電子工学および電気工学

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