Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.
|ジャーナル||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|出版ステータス||Published - 1994 12月 1|
|イベント||Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA|
継続期間: 1994 11月 6 → 1994 11月 10
ASJC Scopus subject areas
- コンピュータ グラフィックスおよびコンピュータ支援設計