Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs with performance optimization

Nozomu Togawa*, Masao Sato, Tatsuo Ohtsuki

*この研究の対応する著者

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

In this paper, we propose a new FPGA design algorithm, Maple-opt, in which technology mapping, placement, and global routing are executed so that the delay of each critical signal path in an input circuit is within a specified upper bound imposed on it. The basic algorithm of Maple-opt is top-down hierarchical bi-partitioning of regions. Technology mapping onto logic-blocks of FPGAs, their placement, and global routing are determined simultaneously in each hierarchical process. This simultaneity leads to less congested layout for routing. In addition to that, Maple-opt computes a lower bound of delay for each path with a constraint value and determines critical paths based on the difference between the lower bound and the constraint value dynamically in each hierarchical process. Two delay reduction processes are executed for the critical paths; one is routing delay reduction and the other is logic-block delay reduction. Routing delay reduction is realized such that, when bi-partitioning a region, each constrained path is assigned to one subregion. Logic-block delay reduction is realized such that each constrained path is mapped onto fewer logic-blocks. Experimental results for some benchmark circuits show its efficiency and effectiveness.

本文言語English
ページ319-327
ページ数9
出版ステータスPublished - 1995 12 1
イベントProceedings of the 1995 Asia and South Pacific Design Automation Conference, ASP-DAC'95 - Chiba, Jpn
継続期間: 1995 8 291995 9 1

Other

OtherProceedings of the 1995 Asia and South Pacific Design Automation Conference, ASP-DAC'95
CityChiba, Jpn
Period95/8/2995/9/1

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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