Memory design using a one-transistor gain cell on SOI

Takashi Ohsawa*, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiyuki Asao, Kazumasa Sunouchi

*この研究の対応する著者

研究成果: Article査読

54 被引用数 (Scopus)

抄録

A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F2(F = 0.18 μm) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F2 cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and Cb/Cs free signal development drastically improve cell efficiency.

本文言語English
ページ(範囲)1510-1522
ページ数13
ジャーナルIEEE Journal of Solid-State Circuits
37
11
DOI
出版ステータスPublished - 2002 11月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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