Memory-efficient accelerating schedule for LDPC decoder

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

抜粋

This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

元の言語English
ホスト出版物のタイトルAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
ページ1317-1320
ページ数4
DOI
出版物ステータスPublished - 2006 12 1
イベントAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
継続期間: 2006 12 42006 12 6

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Singapore
期間06/12/406/12/6

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Shimizu, K., Togawa, N., Ikenaga, T., & Goto, S. (2006). Memory-efficient accelerating schedule for LDPC decoder. : APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 1317-1320). [4145643] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342426