Chip Multiprocessor (CMP) architecture has attracting much attention as a next-generation microprocessor architecture and many kinds of CMP are widely being researched. However, CMP architectures several difficulties for effective use of memory, especially cache or local memory near a processor core. The authors have proposed OSCAR CMP architecture, which cooperatively works with multigrain parallelizing compiler which gives us much higher parallelism than instruction level parallelism or loop level parallelism and high productivity of application programs. To support the compiler optimization for effective use of cache or local memory, OSCAR CMP has local data memory (LDM) for processor private data and distributed shared memory (DSM) for synchronization and fine grain data transfers among processors, in addition to centralized shared memory (CSM) to support dynamic task scheduling. This paper proposes a static coarse grain task scheduling scheme for data localization using live variable analysis. Furthermore, remote memory data transfer scheduling scheme using information of live variable analysis is also described. The proposed scheme is implemented on OSCAR FORTRAN multigrain parallelizing compiler and is evaluated on OSCAR CMP using Tomcatv and Swim in SPEC CFP 95 benchmark.
|出版ステータス||Published - 2004|
|イベント||Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004 - Maui, HI, United States|
継続期間: 2004 1 12 → 2004 1 14
|Conference||Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2004|
|Period||04/1/12 → 04/1/14|
ASJC Scopus subject areas
- コンピュータ サイエンス（全般）