TY - JOUR
T1 - Message-based efficient remote memory access on a highly parallel computer EM-X
AU - Kodama, Yuetsu
AU - Sakane, Hirohumi
AU - Mitsuhisa Sato, N.
AU - Yamana, Hayato
AU - Sakal, Shuichi
AU - Yamaguchl, Yoshinori
PY - 1996/1/1
Y1 - 1996/1/1
N2 - Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The prioritybased scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.
AB - Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The prioritybased scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.
KW - Distributed shared memory
KW - Fine grain communication
KW - Mitltithread architecture
UR - http://www.scopus.com/inward/record.url?scp=0030219318&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030219318&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0030219318
VL - E79-D
SP - 1065
EP - 1071
JO - IEICE Transactions on Information and Systems
JF - IEICE Transactions on Information and Systems
SN - 0916-8532
IS - 8
ER -