Message-based efficient remote memory access on a highly parallel computer EM-X

Yuetsu Kodama, Hirohumi Sakane, N. Mitsuhisa Sato, Hayato Yamana, Shuichi Sakal, Yoshinori Yamaguchl

研究成果: Article査読

抄録

Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The prioritybased scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.

本文言語English
ページ(範囲)1065-1071
ページ数7
ジャーナルIEICE Transactions on Information and Systems
E79-D
8
出版ステータスPublished - 1996 1 1
外部発表はい

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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