MeV-BORON IMPLANTED BURIED BARRIER FOR SOFT ERROR REDUCTION IN MEGABIT DRAM.

Y. Matsuda, K. Tsukamoto, M. Inuishi, M. Shimizu, M. Asakura, K. Fujishima, J. Komori, Y. Akasaka

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

The soft error rate (SER) reduction by an MeV-boron implanted buried barrier is presented in applying a 1Mbit NMOS DRAM. Improvement by a factor of more than X100 was obtained in the bit line mode SER and also by a factor of X50 in the cell mode SER compared with the HiC structure. With the aid of the buried barrier, less than 100 FIT of the SER would be achieved in megabit DRAM with the storage capacitance of 24fF at 5V operation.

本文言語English
ホスト出版物のタイトルConference on Solid State Devices and Materials
出版社Japan Soc of Applied Physics
ページ23-26
ページ数4
ISBN(印刷版)4930813212, 9784930813213
DOI
出版ステータスPublished - 1987
外部発表はい

出版物シリーズ

名前Conference on Solid State Devices and Materials

ASJC Scopus subject areas

  • Engineering(all)

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