The soft error rate (SER) reduction by an MeV-boron implanted buried barrier is presented in applying a 1Mbit NMOS DRAM. Improvement by a factor of more than X100 was obtained in the bit line mode SER and also by a factor of X50 in the cell mode SER compared with the HiC structure. With the aid of the buried barrier, less than 100 FIT of the SER would be achieved in megabit DRAM with the storage capacitance of 24fF at 5V operation.
|ホスト出版物のタイトル||Conference on Solid State Devices and Materials|
|出版社||Japan Soc of Applied Physics|
|出版ステータス||Published - 1987|
|名前||Conference on Solid State Devices and Materials|
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