抄録
In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 1414-1422 |
| ページ数 | 9 |
| ジャーナル | IEICE Electronics Express |
| 巻 | 9 |
| 発行部数 | 17 |
| DOI | |
| 出版物ステータス | Published - 2012 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
これを引用
MH 4 : Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures. / Abe, Shin Ya; Shi, Youhua; Yanagisawa, Masao; Togawa, Nozomu.
：: IEICE Electronics Express, 巻 9, 番号 17, 2012, p. 1414-1422.研究成果: Article
}
TY - JOUR
T1 - MH 4
T2 - Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures
AU - Abe, Shin Ya
AU - Shi, Youhua
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2012
Y1 - 2012
N2 - In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.
AB - In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.
KW - Distributed-register architecture
KW - Energy-optimization
KW - High-level synthesis
KW - Interconnection delay
KW - Multiple supply voltages
UR - http://www.scopus.com/inward/record.url?scp=84869078009&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84869078009&partnerID=8YFLogxK
U2 - 10.1587/elex.9.1414
DO - 10.1587/elex.9.1414
M3 - Article
AN - SCOPUS:84869078009
VL - 9
SP - 1414
EP - 1422
JO - IEICE Electronics Express
JF - IEICE Electronics Express
SN - 1349-2543
IS - 17
ER -