MH 4: Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures

    研究成果: Article

    14 引用 (Scopus)

    抄録

    In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.

    元の言語English
    ページ(範囲)1414-1422
    ページ数9
    ジャーナルIEICE Electronics Express
    9
    発行部数17
    DOI
    出版物ステータスPublished - 2012

    Fingerprint

    Networks (circuits)
    synthesis
    clocks
    iteration
    High level synthesis
    Clocks
    high voltages
    high speed
    Electric potential
    estimates
    Chemical analysis

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering

    これを引用

    @article{2890f2ae512c4c8cba76b6e06c385215,
    title = "MH 4: Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures",
    abstract = "In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29{\%} run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.",
    keywords = "Distributed-register architecture, Energy-optimization, High-level synthesis, Interconnection delay, Multiple supply voltages",
    author = "Abe, {Shin Ya} and Youhua Shi and Masao Yanagisawa and Nozomu Togawa",
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    publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
    number = "17",

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    TY - JOUR

    T1 - MH 4

    T2 - Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures

    AU - Abe, Shin Ya

    AU - Shi, Youhua

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2012

    Y1 - 2012

    N2 - In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.

    AB - In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning- directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given.

    KW - Distributed-register architecture

    KW - Energy-optimization

    KW - High-level synthesis

    KW - Interconnection delay

    KW - Multiple supply voltages

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