Minimization of fractional wordlength on fixed-point conversion for high-level synthesis

Nobuhiro Doi*, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura

*この研究の対応する著者

研究成果: Paper査読

18 被引用数 (Scopus)

抄録

In the hardware synthesis from high-level language such as C, bit length of variables is one of the key issues on the area and speed optimization. Usually, designers are required to specify the word length of each variable manually, and verify the correctness by the simulation on huge data. In this paper, we propose an optimization method of fractional wold length of floating-point variables in the floating to fixed-point conversion of variables. The amount of round-off errors are formulated with parameters and propagated via data flow graphs. The non-linear programming is used to solve the fractional wordlength minimization problem. The method does not require the simulation on huge data, and is very fast compared to ones based on the simulation. We have shown the effect on several programs.

本文言語English
ページ80-85
ページ数6
出版ステータスPublished - 2004 6月 1
イベントProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
継続期間: 2004 1月 272004 1月 30

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
国/地域Japan
CityYokohama
Period04/1/2704/1/30

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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