Mixed bus width architecture for low cost AES VLSI design

Yibo Fan*, Jidong Wang, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

抄録

With the increase of security problem, AES is widely used in a lot of secure systems. For some low data throughput applications, low cost design is more attractive than high speed design. In this paper, low cost hardware architecture for AES algorithm is proposed. Mixed bus width architecture is used to reduce hardware cost and shorten critical path. The experimental results show that the lowest hardware cost implementation of AES algorithm is 4678 Gates. The corresponding frequency is 80MHz and the throughput is 51Mbps. This architecture is very suitable for mid-throughput, low power and low hardware cost systems such as mobile system.

本文言語English
ホスト出版物のタイトルASICON 2007 - 2007 7th International Conference on ASIC Proceeding
ページ854-857
ページ数4
DOI
出版ステータスPublished - 2007 12 1
イベント2007 7th International Conference on ASIC, ASICON 2007 - Guilin, China
継続期間: 2007 10 262007 10 29

出版物シリーズ

名前ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Conference

Conference2007 7th International Conference on ASIC, ASICON 2007
国/地域China
CityGuilin
Period07/10/2607/10/29

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

フィンガープリント

「Mixed bus width architecture for low cost AES VLSI design」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル