Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies

Zhangcai Huang*, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue

*この研究の対応する著者

    研究成果: Article査読

    40 被引用数 (Scopus)

    抄録

    With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

    本文言語English
    論文番号5395729
    ページ(範囲)250-260
    ページ数11
    ジャーナルIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    29
    2
    DOI
    出版ステータスPublished - 2010 2月

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • コンピュータ グラフィックスおよびコンピュータ支援設計
    • ソフトウェア

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