With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.
|ホスト出版物のタイトル||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|
|出版ステータス||Published - 2007|
|イベント||ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama|
継続期間: 2007 1 23 → 2007 1 27
|Other||ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007|
|Period||07/1/23 → 07/1/27|
ASJC Scopus subject areas