Modeling the overshooting effect for CMOS inverter in nanometer technologies

Huang Zhangcai; Yu Hong; Atsushi Kurokawa; Yasuaki Inoue

doi:10.1109/ASPDAC.2007.358046

Modeling the overshooting effect for CMOS inverter in nanometer technologies

Huang Zhangcai^*, Yu Hong, Atsushi Kurokawa, Yasuaki Inoue

^*この研究の対応する著者

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

本文言語	English
ホスト出版物のタイトル	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ	565-570
ページ数	6
DOI	https://doi.org/10.1109/ASPDAC.2007.358046
出版ステータス	Published - 2007
イベント	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama 継続期間: 2007 1月 23 → 2007 1月 27

Other

Other	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
City	Yokohama
Period	07/1/23 → 07/1/27

ASJC Scopus subject areas

工学（全般）

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10.1109/ASPDAC.2007.358046

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引用スタイル

Zhangcai, H, Hong, Y, Kurokawa, A & Inoue, Y 2007, Modeling the overshooting effect for CMOS inverter in nanometer technologies. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4196092, pp. 565-570, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, 07/1/23. https://doi.org/10.1109/ASPDAC.2007.358046

@inproceedings{8287ab22b66b44bf811e9ebf92a3ecd0,

title = "Modeling the overshooting effect for CMOS inverter in nanometer technologies",

abstract = "With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.",

author = "Huang Zhangcai and Yu Hong and Atsushi Kurokawa and Yasuaki Inoue",

year = "2007",

doi = "10.1109/ASPDAC.2007.358046",

language = "English",

isbn = "1424406293",

pages = "565--570",

booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

note = "ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 ; Conference date: 23-01-2007 Through 27-01-2007",

}

TY - GEN

T1 - Modeling the overshooting effect for CMOS inverter in nanometer technologies

AU - Zhangcai, Huang

AU - Hong, Yu

AU - Kurokawa, Atsushi

AU - Inoue, Yasuaki

PY - 2007

Y1 - 2007

N2 - With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

AB - With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

UR - http://www.scopus.com/inward/record.url?scp=46649121035&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46649121035&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2007.358046

DO - 10.1109/ASPDAC.2007.358046

M3 - Conference contribution

AN - SCOPUS:46649121035

SN - 1424406293

SN - 9781424406296

SP - 565

EP - 570

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

T2 - ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007

Y2 - 23 January 2007 through 27 January 2007

ER -

Modeling the overshooting effect for CMOS inverter in nanometer technologies

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