Modeling the overshooting effect for CMOS inverter in nanometer technologies

Huang Zhangcai*, Yu Hong, Atsushi Kurokawa, Yasuaki Inoue

*この研究の対応する著者

    研究成果: Conference contribution

    8 被引用数 (Scopus)

    抄録

    With the scaling of CMOS technology, the over-shooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

    本文言語English
    ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    ページ565-570
    ページ数6
    DOI
    出版ステータスPublished - 2007
    イベントASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama
    継続期間: 2007 1 232007 1 27

    Other

    OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
    CityYokohama
    Period07/1/2307/1/27

    ASJC Scopus subject areas

    • 工学(全般)

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