Modeling the overshooting effect of multi-input gate in nanometer technologies

Li Ding*, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

*この研究の対応する著者

    研究成果: Article査読

    1 被引用数 (Scopus)

    抄録

    With the advent of nanometer age in digital circuits, the overshooting time becomes an important component of gate delay for CMOS logic gates. However, there has been little attention paid to the research of the overshooting effect for multi-input gate in nanometer technologies until now. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32-nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

    本文言語English
    論文番号1240012
    ジャーナルJournal of Circuits, Systems and Computers
    21
    6
    DOI
    出版ステータスPublished - 2012 10

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • ハードウェアとアーキテクチャ

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