Modeling the overshooting effect of multi-input gate in nanometer technologies

Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue

    研究成果: Conference contribution

    3 引用 (Scopus)

    抜粋

    With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

    元の言語English
    ホスト出版物のタイトルMidwest Symposium on Circuits and Systems
    DOI
    出版物ステータスPublished - 2011
    イベント54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul
    継続期間: 2011 8 72011 8 10

    Other

    Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
    Seoul
    期間11/8/711/8/10

      フィンガープリント

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    これを引用

    Ding, L., Huang, Z., Jiang, M., Kurokawa, A., & Inoue, Y. (2011). Modeling the overshooting effect of multi-input gate in nanometer technologies. : Midwest Symposium on Circuits and Systems [6026587] https://doi.org/10.1109/MWSCAS.2011.6026587