Motion compensation architecture for 8K UHDTV HEVC decoder

Shihao Wang, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    9 引用 (Scopus)

    抜粋

    This paper presents a motion compensation (MC) architecture for 8K UHDTV HEVC video decoder. UHDTV's high resolution significantly increases throughput and memory traffic. Moreover, HEVC supports new coding tools like various sizes of coding unit ranging from 8 to 64. To solve these problems, we propose three optimization schemes. Firstly, four-bank parallel 2D cache organization is proposed to reduce 61.86% memory traffic and support higher interpolator throughput for HEVC. Secondly, we propose pipelined Write-Through mechanism (WTM) to achieve conflict-free performance. Moreover, WTM scheme contributes to around 50% reduction on both memory area and logic gate. Finally, highly parallel interpolator with proposed cache forms integral structure supporting UHDTV. In 90nm process, our design cost 103.6k logic gates with 12kB cache memory. The proposed architecture can support real-time decoding 7680×4320@30fps at 280MHz.

    元の言語English
    ホスト出版物のタイトルProceedings - IEEE International Conference on Multimedia and Expo
    出版者IEEE Computer Society
    2014-September
    エディションSeptmber
    DOI
    出版物ステータスPublished - 2014 9 3
    イベント2014 IEEE International Conference on Multimedia and Expo, ICME 2014 - Chengdu, China
    継続期間: 2014 7 142014 7 18

    Other

    Other2014 IEEE International Conference on Multimedia and Expo, ICME 2014
    China
    Chengdu
    期間14/7/1414/7/18

      フィンガープリント

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Computer Science Applications

    これを引用

    Wang, S., Zhou, D., & Goto, S. (2014). Motion compensation architecture for 8K UHDTV HEVC decoder. : Proceedings - IEEE International Conference on Multimedia and Expo (Septmber 版, 巻 2014-September). [6890221] IEEE Computer Society. https://doi.org/10.1109/ICME.2014.6890221