Multi-cycle path detection based on propositional satisfiability with CNF simplification using adaptive variable insertion

Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsurnasa Watanabe

研究成果: Article査読

4 被引用数 (Scopus)

抄録

Multi-cycle paths are paths between registers where 2 or more clock cycles are allowed to propagate signals, and the detection of multi-cycle paths is important in deciding proper clock period, timing verification and logic optimization. This paper presents a satisfiability-based multi-cycle path detection method, where the detection problems are reduced to CNF formulae and the satisfiability is checked using SAT provers. We also show heuristics on conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS'89 benchmarks and other sample circuits. Experimental results show the remarkable improvements on the size of manipulatable circuits.

本文言語English
ページ(範囲)2600-2607
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E83-A
12
出版ステータスPublished - 2000 12
外部発表はい

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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