Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints

Song Chen*, Takeshi Yoshimura

*この研究の対応する著者

研究成果: Article査読

19 被引用数 (Scopus)

抄録

3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.

本文言語English
ページ(範囲)378-388
ページ数11
ジャーナルIntegration, the VLSI Journal
43
4
DOI
出版ステータスPublished - 2010 9月

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • ソフトウェア
  • 電子工学および電気工学

引用スタイル