Multi-operand adder synthesis on FPGAs using generalized parallel counters

Taeko Matsunaga*, Shinji Kimura, Yusuke Matsunaga

*この研究の対応する著者

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

Multi-operand adders usually consist of compression trees which reduce the number of operands per a bit to two, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compression trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show its effectiveness against existing approaches at GPC level and on Altera's Stratix III.

本文言語English
ホスト出版物のタイトル2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
ページ337-342
ページ数6
DOI
出版ステータスPublished - 2010
イベント2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan, Province of China
継続期間: 2010 1月 182010 1月 21

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
国/地域Taiwan, Province of China
CityTaipei
Period10/1/1810/1/21

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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