Multi-operand adder synthesis on FPGAs using generalized parallel counters

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga

研究成果: Conference contribution

8 引用 (Scopus)

抄録

Multi-operand adders usually consist of compression trees which reduce the number of operands per a bit to two, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compression trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show its effectiveness against existing approaches at GPC level and on Altera's Stratix III.

元の言語English
ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ337-342
ページ数6
DOI
出版物ステータスPublished - 2010
イベント2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei
継続期間: 2010 1 182010 1 21

Other

Other2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Taipei
期間10/1/1810/1/21

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Adders
Field programmable gate arrays (FPGA)
Application specific integrated circuits
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

これを引用

Matsunaga, T., Kimura, S., & Matsunaga, Y. (2010). Multi-operand adder synthesis on FPGAs using generalized parallel counters. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 337-342). [5419871] https://doi.org/10.1109/ASPDAC.2010.5419871

Multi-operand adder synthesis on FPGAs using generalized parallel counters. / Matsunaga, Taeko; Kimura, Shinji; Matsunaga, Yusuke.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2010. p. 337-342 5419871.

研究成果: Conference contribution

Matsunaga, T, Kimura, S & Matsunaga, Y 2010, Multi-operand adder synthesis on FPGAs using generalized parallel counters. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 5419871, pp. 337-342, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, 10/1/18. https://doi.org/10.1109/ASPDAC.2010.5419871
Matsunaga T, Kimura S, Matsunaga Y. Multi-operand adder synthesis on FPGAs using generalized parallel counters. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2010. p. 337-342. 5419871 https://doi.org/10.1109/ASPDAC.2010.5419871
Matsunaga, Taeko ; Kimura, Shinji ; Matsunaga, Yusuke. / Multi-operand adder synthesis on FPGAs using generalized parallel counters. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2010. pp. 337-342
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