Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

研究成果: Article査読

抄録

Multi-scenario high-level synthesis for distributed register/controller architecture has been proposed targeting static delay variation. In this paper, we extend it and propose a floorplan-driven high-level synthesis algorithm which can be applied to dynamic delay variation by effectively using an error prediction technique, where pre-error registers are introduced to local registers in every circuit block. Experimental results show that the proposed algorithm using two and three scenarios on an FPGA chip reduces the average number of required control steps by 17.6% and 25.5% on average compared to worst-case high-level synthesis at the expense of increasing lookup-tables and flip-flops. Moreover, we implement a multi-scenario elliptic-wave-filter (EWF) circuit with three scenarios synthesized by our proposed algorithm onto an FPGA chip and run it under the environment with varying supply voltages which causes dynamic delay variation. The FPGA implementation experiments also demonstrate that the EWF circuit effectively runs on the real FPGA chip. As far as we know, this is the world-first experiment where a multi-scenario circuit runs under real dynamic delay variation environment.

本文言語English
論文番号20160641
ジャーナルieice electronics express
13
18
DOI
出版ステータスPublished - 2016

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 凝縮系物理学
  • 電子工学および電気工学

フィンガープリント

「Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル