Multiple network-on-chip model for high performance neural network

Yiping Dong*, Ce Li, Zhen Lin, Takahiro Watanabe

*この研究の対応する著者

研究成果: Article査読

10 被引用数 (Scopus)

抄録

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

本文言語English
ページ(範囲)28-36
ページ数9
ジャーナルJournal of Semiconductor Technology and Science
10
1
DOI
出版ステータスPublished - 2010 3月

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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