Along with the progress of the information society, we are relying more and more on digital information processing with security. Cryptography plays an important role in a situation where unwanted eavesdropping or falsification has to be avoided. Public key encryptions including RSA require a huge number of arithmetic operations. Major part of its operation is modular multiplication with very large bit-width. This operation takes long time, and there is an advantage in hardware implementation of it. We propose the hardware implementation of N-bit-wise multiplier. It allows the operation performed at the speed 2 times the original performance for the same circuit size, or the circuit size reduced to approximately 60% for the same processing time. Employing the architecture proposed in this paper contributes to the performance improvement of encryption system and the reduction of chip size of encryption system.
|ジャーナル||Proceedings - International Carnahan Conference on Security Technology|
|出版ステータス||Published - 2004 12月 1|
|イベント||Proceedings - IEEE 38th Annual 2004 International Carnahan Conference on Security Technology - Albuquerque, NM, United States|
継続期間: 2004 10月 11 → 2004 10月 14
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