Network flow-based simultaneous retiming and slack budgeting for low power design

Bei Yu*, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs) across logic gates to achieve faster clocking speed. In this paper we show that the retiming and slack budgeting problem can be formulated to a convex cost dual network flow problem. Both the theoretical analysis and experimental results show the efficiency of our approach which can not only reduce power consumption by 8.9%, but also speedup previous work by 500 times.

本文言語English
ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ473-478
ページ数6
DOI
出版ステータスPublished - 2011
イベント2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama
継続期間: 2011 1月 252011 1月 28

Other

Other2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CityYokohama
Period11/1/2511/1/28

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計

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