Network on chip architecture for BP neural network

Yiping Dong*, Takahiro Watanabe

*この研究の対応する著者

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

Recently, Networks-on-Chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of Artificial Neural Networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (Back-Propagation) and evaluated by Network-on-Chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.

本文言語English
ホスト出版物のタイトル2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
ページ964-968
ページ数5
DOI
出版ステータスPublished - 2008
外部発表はい
イベント2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China
継続期間: 2008 5月 252008 5月 27

出版物シリーズ

名前2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Conference

Conference2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
国/地域China
CityXiamen, Fujian Province
Period08/5/2508/5/27

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • ハードウェアとアーキテクチャ
  • 制御およびシステム工学
  • 電子工学および電気工学

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