To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in . The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In , a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.
|ジャーナル||Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon|
|出版ステータス||Published - 1995 1 1|
|イベント||Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA|
継続期間: 1995 1 18 → 1995 1 20
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