TY - JOUR
T1 - Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches
AU - Takanami, Itsuo
AU - Kurata, Kazushi
AU - Watanabe, Takahiro
PY - 1995/1/1
Y1 - 1995/1/1
N2 - To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.
AB - To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.
UR - http://www.scopus.com/inward/record.url?scp=0029235214&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0029235214&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0029235214
SN - 1063-2204
SP - 101
EP - 110
JO - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
JF - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
T2 - Proceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration
Y2 - 18 January 1995 through 20 January 1995
ER -