Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

Itsuo Takanami*, Kazushi Kurata, Takahiro Watanabe

*この研究の対応する著者

研究成果: Conference article査読

17 被引用数 (Scopus)

抄録

To overcome faults in mesh-connected processor arrays, a number of reconfiguration schemes have been studied in the literature. As one of them, the mesh-connected processor arrays model based on single-track switches has been proposed in [1]. The model has an advantage of its inherent simplicity of the routing hardware. So far, some algorithms have been proposed to solve the problem of reconfiguration for this model. In [2], a polynomial time algorithm has been presented. However, it needs a global information on fault distribution and it seems to be a troublesome job to implement the algorithm even by software while it may be impossible to implement it by hardware. In this paper, using Hopfield-type neural network model, we present an algorithm for reconstructing the mesh-connected processor arrays using single-track switches and show its effectiveness by computer simulation. Furthermore, we present a hardware implementation of the neural algorithm by which a self-repair system can be realized.

本文言語English
ページ(範囲)101-110
ページ数10
ジャーナルProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
出版ステータスPublished - 1995 1 1
外部発表はい
イベントProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
継続期間: 1995 1 181995 1 20

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 凝縮系物理学

フィンガープリント

「Neural algorithm for reconstructing mesh-connected processor arrays using single-track switches」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル