NEW ARCHITECTURE FOR THE NVRAM - AN EEPROM BACKED - UP DYNAMIC RAM.

Yasushi Terada*, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara

*この研究の対応する著者

研究成果: Article査読

抄録

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.

本文言語English
ジャーナルIEEE Journal of Solid-State Circuits
23
1
出版ステータスPublished - 1987 2
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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