New incremental simulation algorithm for large scale circuits and its evaluation

Hiroshi Arai, Yoshiaki Fukazawa

研究成果: Conference contribution

2 引用 (Scopus)

抄録

The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net's simulation events. Compared to traditional net selection algorithm, speedups of 1.78 to 1.94 were achievable with our algorithm.

元の言語English
ホスト出版物のタイトルIEEE Region 10 Annual International Conference, Proceedings/TENCON
出版場所Piscataway, NJ, United States
出版者IEEE
ページ343-346
ページ数4
出版物ステータスPublished - 1995
外部発表Yes
イベントProceedings of the 1995 IEEE Region 10 International Conference on Microelectronics and VLSI, TENCON'95 - Hong Kong, Hong Kong
継続期間: 1995 11 61995 11 10

Other

OtherProceedings of the 1995 IEEE Region 10 International Conference on Microelectronics and VLSI, TENCON'95
Hong Kong, Hong Kong
期間95/11/695/11/10

Fingerprint

Networks (circuits)
Hardware

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Arai, H., & Fukazawa, Y. (1995). New incremental simulation algorithm for large scale circuits and its evaluation. : IEEE Region 10 Annual International Conference, Proceedings/TENCON (pp. 343-346). Piscataway, NJ, United States: IEEE.

New incremental simulation algorithm for large scale circuits and its evaluation. / Arai, Hiroshi; Fukazawa, Yoshiaki.

IEEE Region 10 Annual International Conference, Proceedings/TENCON. Piscataway, NJ, United States : IEEE, 1995. p. 343-346.

研究成果: Conference contribution

Arai, H & Fukazawa, Y 1995, New incremental simulation algorithm for large scale circuits and its evaluation. : IEEE Region 10 Annual International Conference, Proceedings/TENCON. IEEE, Piscataway, NJ, United States, pp. 343-346, Proceedings of the 1995 IEEE Region 10 International Conference on Microelectronics and VLSI, TENCON'95, Hong Kong, Hong Kong, 95/11/6.
Arai H, Fukazawa Y. New incremental simulation algorithm for large scale circuits and its evaluation. : IEEE Region 10 Annual International Conference, Proceedings/TENCON. Piscataway, NJ, United States: IEEE. 1995. p. 343-346
Arai, Hiroshi ; Fukazawa, Yoshiaki. / New incremental simulation algorithm for large scale circuits and its evaluation. IEEE Region 10 Annual International Conference, Proceedings/TENCON. Piscataway, NJ, United States : IEEE, 1995. pp. 343-346
@inproceedings{e4ee177c45be4af5a4fcaff5f1a57a6e,
title = "New incremental simulation algorithm for large scale circuits and its evaluation",
abstract = "The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net's simulation events. Compared to traditional net selection algorithm, speedups of 1.78 to 1.94 were achievable with our algorithm.",
author = "Hiroshi Arai and Yoshiaki Fukazawa",
year = "1995",
language = "English",
pages = "343--346",
booktitle = "IEEE Region 10 Annual International Conference, Proceedings/TENCON",
publisher = "IEEE",

}

TY - GEN

T1 - New incremental simulation algorithm for large scale circuits and its evaluation

AU - Arai, Hiroshi

AU - Fukazawa, Yoshiaki

PY - 1995

Y1 - 1995

N2 - The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net's simulation events. Compared to traditional net selection algorithm, speedups of 1.78 to 1.94 were achievable with our algorithm.

AB - The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net's simulation events. Compared to traditional net selection algorithm, speedups of 1.78 to 1.94 were achievable with our algorithm.

UR - http://www.scopus.com/inward/record.url?scp=0029519138&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029519138&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029519138

SP - 343

EP - 346

BT - IEEE Region 10 Annual International Conference, Proceedings/TENCON

PB - IEEE

CY - Piscataway, NJ, United States

ER -