抄録
The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net's simulation events. Compared to traditional net selection algorithm, speedups of 1.78 to 1.94 were achievable with our algorithm.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | IEEE Region 10 Annual International Conference, Proceedings/TENCON |
| 出版場所 | Piscataway, NJ, United States |
| 出版者 | IEEE |
| ページ | 343-346 |
| ページ数 | 4 |
| 出版物ステータス | Published - 1995 |
| 外部発表 | Yes |
| イベント | Proceedings of the 1995 IEEE Region 10 International Conference on Microelectronics and VLSI, TENCON'95 - Hong Kong, Hong Kong 継続期間: 1995 11 6 → 1995 11 10 |
Other
| Other | Proceedings of the 1995 IEEE Region 10 International Conference on Microelectronics and VLSI, TENCON'95 |
|---|---|
| 市 | Hong Kong, Hong Kong |
| 期間 | 95/11/6 → 95/11/10 |
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ASJC Scopus subject areas
- Engineering(all)
これを引用
New incremental simulation algorithm for large scale circuits and its evaluation. / Arai, Hiroshi; Fukazawa, Yoshiaki.
IEEE Region 10 Annual International Conference, Proceedings/TENCON. Piscataway, NJ, United States : IEEE, 1995. p. 343-346.研究成果: Conference contribution
}
TY - GEN
T1 - New incremental simulation algorithm for large scale circuits and its evaluation
AU - Arai, Hiroshi
AU - Fukazawa, Yoshiaki
PY - 1995
Y1 - 1995
N2 - The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net's simulation events. Compared to traditional net selection algorithm, speedups of 1.78 to 1.94 were achievable with our algorithm.
AB - The incremental simulation algorithm speeds up the simulation of digital hardware by storing and reusing simulation events. For large circuits, in order to reduce the amount of events to be stored, it is necessary to select nets and store only the events relevant to those nets. Our new incremental simulation algorithm selects nets according to expected amounts of evaluation eliminated by storing each net's simulation events. Compared to traditional net selection algorithm, speedups of 1.78 to 1.94 were achievable with our algorithm.
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UR - http://www.scopus.com/inward/citedby.url?scp=0029519138&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0029519138
SP - 343
EP - 346
BT - IEEE Region 10 Annual International Conference, Proceedings/TENCON
PB - IEEE
CY - Piscataway, NJ, United States
ER -