New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

S. Kobayashi, M. Edahiro, Y. Hayashi

研究成果: Conference contribution

抄録

We present here the use of the performance predicting ECAD system, which is called Layout-design-based Interconnect Structure Optimization System (LADINOS), for the optimization of multilayer interconnect structures. This system is intended to be used to redesign current ULSI data on possible interconnect structures in the future and to measure the performance of such redesigned ULSIs. Despite the fact that system procedures include chip-size prediction, timing-driven assignment of interconnects to layers, and RC extraction which takes coupling capacitance into account, these procedures are performed very fast. We also give an example of the optimization of multi-layer interconnect structures for use in 0.13 μm-generation ULSIs with Al-interconnects.

本文言語English
ホスト出版物のタイトルProceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000
出版社Institute of Electrical and Electronics Engineers Inc.
ページ12-14
ページ数3
ISBN(電子版)0780363272, 9780780363274
DOI
出版ステータスPublished - 2000
外部発表はい
イベント3rd IEEE International Interconnect Technology Conference, IITC 2000 - Burlingame, United States
継続期間: 2000 6 52000 6 7

出版物シリーズ

名前Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000

Conference

Conference3rd IEEE International Interconnect Technology Conference, IITC 2000
国/地域United States
CityBurlingame
Period00/6/500/6/7

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)

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