Nitride-sandwiched-oxide gate insulator for low power CMOS

D. Ishikawa*, S. Sakai, K. Katsuyama, A. Hiraiwa

*この研究の対応する著者

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.

本文言語English
ホスト出版物のタイトルTechnical Digest - International Electron Devices Meeting
ページ869-872
ページ数4
出版ステータスPublished - 2002
外部発表はい
イベント2002 IEEE International Devices Meeting (IEDM) - San Francisco, CA, United States
継続期間: 2002 12 82002 12 11

Other

Other2002 IEEE International Devices Meeting (IEDM)
国/地域United States
CitySan Francisco, CA
Period02/12/802/12/11

ASJC Scopus subject areas

  • 電子工学および電気工学

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