### 抄録

We present an ordered tree, O-tree, structure to represent non-slicing floorplans. We define an admissible placement as a compacted placement in both x and y direction. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n! 2
^{2n-2}/n
^{1.5}). This is very concise compared to a sequence pair representation which has O((n!)
^{2}) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n
^{2} (n/4e)
^{n}). The complexity of O-tree is even smaller than a binary tree structure for slicing floorplan which has O(n! 2
^{5n-3}/n
^{1.5}) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC benchmarks show promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method.

元の言語 | English |
---|---|

ホスト出版物のタイトル | Proceedings - Design Automation Conference |

出版者 | IEEE |

ページ | 268-273 |

ページ数 | 6 |

出版物ステータス | Published - 1999 |

外部発表 | Yes |

イベント | Proceedings of the 1999 36th Annual Design Automation Conference (DAC) - New Orleans, LA, USA 継続期間: 1999 6 21 → 1999 6 25 |

### Other

Other | Proceedings of the 1999 36th Annual Design Automation Conference (DAC) |
---|---|

市 | New Orleans, LA, USA |

期間 | 99/6/21 → 99/6/25 |

### Fingerprint

### ASJC Scopus subject areas

- Hardware and Architecture
- Control and Systems Engineering

### これを引用

*Proceedings - Design Automation Conference*(pp. 268-273). IEEE.

**O-tree representation of non-slicing floorplan and its applications.** / Guo, Pei Ning; Cheng, Chung Kuan; Yoshimura, Takeshi.

研究成果: Chapter

*Proceedings - Design Automation Conference.*IEEE, pp. 268-273, Proceedings of the 1999 36th Annual Design Automation Conference (DAC), New Orleans, LA, USA, 99/6/21.

}

TY - CHAP

T1 - O-tree representation of non-slicing floorplan and its applications

AU - Guo, Pei Ning

AU - Cheng, Chung Kuan

AU - Yoshimura, Takeshi

PY - 1999

Y1 - 1999

N2 - We present an ordered tree, O-tree, structure to represent non-slicing floorplans. We define an admissible placement as a compacted placement in both x and y direction. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n! 2 2n-2/n 1.5). This is very concise compared to a sequence pair representation which has O((n!) 2) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n 2 (n/4e) n). The complexity of O-tree is even smaller than a binary tree structure for slicing floorplan which has O(n! 2 5n-3/n 1.5) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC benchmarks show promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method.

AB - We present an ordered tree, O-tree, structure to represent non-slicing floorplans. We define an admissible placement as a compacted placement in both x and y direction. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n! 2 2n-2/n 1.5). This is very concise compared to a sequence pair representation which has O((n!) 2) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n 2 (n/4e) n). The complexity of O-tree is even smaller than a binary tree structure for slicing floorplan which has O(n! 2 5n-3/n 1.5) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC benchmarks show promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method.

UR - http://www.scopus.com/inward/record.url?scp=0032690067&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032690067&partnerID=8YFLogxK

M3 - Chapter

AN - SCOPUS:0032690067

SP - 268

EP - 273

BT - Proceedings - Design Automation Conference

PB - IEEE

ER -