On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit

H. Notani*, M. Fujii, H. Suzuki, H. Makino, H. Shinohara

*この研究の対応する著者

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (I dn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3σ is within 5% which is our target tolerance for a practical application.

本文言語English
ホスト出版物のタイトルProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
ページ405-408
ページ数4
DOI
出版ステータスPublished - 2008 12 1
外部発表はい
イベント2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
継続期間: 2008 11 32008 11 5

出版物シリーズ

名前Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
国/地域Japan
CityFukuoka
Period08/11/308/11/5

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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