On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

M. Fujii*, H. Suzuki, H. Notani, H. Makino, H. Shinohara

*この研究の対応する著者

研究成果

3 被引用数 (Scopus)

抄録

This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.

本文言語English
ホスト出版物のタイトルESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
ページ258-261
ページ数4
DOI
出版ステータスPublished - 2008 12 31
外部発表はい
イベント34th European Solid-State Circuits Conference, ESSCIRC 2008 - Edinburgh, Scotland, United Kingdom
継続期間: 2008 9 152008 9 19

出版物シリーズ

名前ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Other

Other34th European Solid-State Circuits Conference, ESSCIRC 2008
国/地域United Kingdom
CityEdinburgh, Scotland
Period08/9/1508/9/19

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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