To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.
|ジャーナル||Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)|
|出版ステータス||Published - 1988 9|
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