On-chip multibit-test scheme for VLSI memories

Hideto Hidaka*, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Yasumasa Nishimura, Tsutomu Yoshihara

*この研究の対応する著者

研究成果査読

抄録

To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.

本文言語English
ページ(範囲)78-87
ページ数10
ジャーナルElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
71
9
出版ステータスPublished - 1988 9
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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