This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0. 6 mu s per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are shown. These examples illustrate the high efficiency of the developed DSP device.
|ジャーナル||IEEE Journal on Selected Areas in Communications|
|出版物ステータス||Published - 1985 3|
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering