抜粋
This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0. 6 mu s per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are shown. These examples illustrate the high efficiency of the developed DSP device.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 357-368 |
| ページ数 | 12 |
| ジャーナル | IEEE Journal on Selected Areas in Communications |
| 巻 | SAC-3 |
| 発行部数 | 2 |
| 出版物ステータス | Published - 1985 3 |
フィンガープリント
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering
これを引用
Gambe, H., Ikezawa, T., Matsumura, T., Tsuda, T., & Fujii, S. (1985). ON THE DESIGN OF A HIGH-PERFORMANCE LSI CIRCUIT DIGITAL SIGNAL PROCESSOR FOR COMMUNICATION. IEEE Journal on Selected Areas in Communications, SAC-3(2), 357-368.