3-D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3-D IC floorplanning. It is proved that the number of configuration of 3-D floorplans is less than that of planar floorplans. Sequence Pair is extended (P-SP) to represent 3-D IC floorplans. A new solution perturbation method Remove and Insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method.
|ホスト出版物のタイトル||IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|
|出版物ステータス||Published - 2006|
|イベント||APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - |
継続期間: 2006 12 4 → 2006 12 6
|Other||APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems|
|期間||06/12/4 → 06/12/6|
ASJC Scopus subject areas