On the number of 3-D IC floorplan configurations and a solution perturbation method with good convergence

Song Chen, Takeshi Yoshimura

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

3-D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3-D IC floorplanning. It is proved that the number of configuration of 3-D floorplans is less than that of planar floorplans. Sequence Pair is extended (P-SP) to represent 3-D IC floorplans. A new solution perturbation method Remove and Insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method.

元の言語English
ホスト出版物のタイトルIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
ページ1867-1870
ページ数4
DOI
出版物ステータスPublished - 2006
イベントAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems -
継続期間: 2006 12 42006 12 6

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
期間06/12/406/12/6

    フィンガープリント

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Chen, S., & Yoshimura, T. (2006). On the number of 3-D IC floorplan configurations and a solution perturbation method with good convergence. : IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 1867-1870). [4145779] https://doi.org/10.1109/APCCAS.2006.342203