Optimization of area and power in multi-mode power gating scheme for static memory elements

Xing Su, Shinji Kimura

研究成果: Conference contribution

抄録

This paper presents an optimization method of area and power for static memory elements by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces the usual 5-transistor one to effectively reduce on chip area overhead and leakage power, simultaneously combining trimming circuits (TC) to guarantee the safety of data retention. When applying the proposed approach into clean/dirty-cache (CD-cache), we can reduce area overhead and leakage power consumption. The simulation results show that the area overhead of SRAM with the proposed approach is reduced from 33.4% to 21.8% compared to that of SRAM with usual MMPG. On the other hand, leakage power is reduced by 12.35% compared to SRAM with usual MMPG and by 86.77% compared to SRAM without power gating scheme. Moreover, the ability of noise immunity of SRAM with proposed approach can also be improved.

本文言語English
ホスト出版物のタイトル2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ページ214-217
ページ数4
ISBN(電子版)9781509015702
DOI
出版ステータスPublished - 2017 1 3
イベント2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
継続期間: 2016 10 252016 10 28

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16/10/2516/10/28

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing

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