Optimized design for high-performance megabit DRAMs

Masaki Kumanoya*, Katsumi Dosaka, Yashuhiro Konishi, Tsutomu Yoshihara, Hideshi Miyatake, Yuto Ikeda, Isao Furuta

*この研究の対応する著者

研究成果: Article査読

抄録

Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

本文言語English
ページ(範囲)14-23
ページ数10
ジャーナルElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
72
8
出版ステータスPublished - 1989 8
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「Optimized design for high-performance megabit DRAMs」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル