Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory

Yoshikazu Miyawaki, Takeshi Nakayama, Masaaki Mihara, Shinji Kawai, Minoru Ohkawa, Natsuo Ajika, Masahiro Hatanaka, Yasushi Terada, Tsutomu Yoshihara

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The paper presents an over erasure detection technique. The source line bias scheme in the erase sequence extends the lower limit of threshold voltage detection. With the use of the overerase recover programming, a very tight distribution of the erased state threshold voltage can be obtained without the utilization of a negative voltage. This technique can become one of the key techniques for future generation low voltage flash memories.

本文言語English
ホスト出版物のタイトルIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Place of PublicationPiscataway, NJ, United States
出版社IEEE
ページ63-64
ページ数2
出版ステータスPublished - 1994
外部発表はい
イベントProceedings of the 1994 Symposium on VLSI Circuits - Honolulu, HI, USA
継続期間: 1994 6 91994 6 11

Other

OtherProceedings of the 1994 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period94/6/994/6/11

ASJC Scopus subject areas

  • Engineering(all)

フィンガープリント 「Over-erasure detection technique for tightening Vth distribution for low voltage operation NOR type flash memory」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル