Parallel Architecture for Generalized LFSR in LSI Built-in Self Testing

Tomoko K. Matsushima*, Toshiyasu Matsushima, Shigeichi Hirasawa


研究成果: Article査読


This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with H5 inputs is designed by parallelizing a GLFSR(6, m), where 6 is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSRbased signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e.g., SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with H6 inputs requires less complex hardware than either single GLFSR(H5, m)s or a parallel construction of the H original GLFSR(c5, m)s. It is also shown that the proposed signature analyzer, while requiring simpler hardware, has comparable aliasing probability with analyzers using conventional GLFSRs for some CUT error models of the same test response length and test time. The proposed technique would be practical for testing CUTs with a large number of output sequences, since the test circuit occupies a smaller area on the LSI chip than the conventional multiple-input signature analyzers of comparable aliasing probability.

ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
出版ステータスPublished - 1998 1月 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学


「Parallel Architecture for Generalized LFSR in LSI Built-in Self Testing」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。