Parallel encoder and decoder architecture for cyclic codes

Tomoko K. Matsushima*, Toshiyasu Matsushima, Shigeichi Hirasawa


研究成果: Article査読

21 被引用数 (Scopus)


Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operations, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows // symbols to be processed in parallel, where // is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols /J. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of// conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with //, the proposed architecture is more efficient than a setup using // conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
出版ステータスPublished - 1996 1月 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学


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